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| SN74LS165 8-Bit Parallel-to-Serial Shift Register The SN74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V C mA mA 16 1 http://onsemi.com LOW POWER SCHOTTKY PLASTIC N SUFFIX CASE 648 16 1 SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device SN74LS165N SN74LS165D Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel (c) Semiconductor Components Industries, LLC, 1999 1 December, 1999 - Rev. 6 Publication Order Number: SN74LS165/D SN74LS165 CONNECTION DIAGRAM DIP (TOP VIEW) VCC 16 CP2 15 P3 14 P2 13 P1 12 P0 11 DS 10 Q7 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 1 PL 2 CP1 3 P4 4 P5 5 P6 6 P7 7 Q7 8 GND LOADING (Note a) PIN NAMES CP1, CP2 DS PL P0 - P7 Q7 Q7 Clock (LOW-to-HIGH Going Edge) Inputs Serial Data Input Asynchronous Parallel Load (Active LOW) Input Parallel Data Inputs Serial Output from Last State Complementary Output HIGH 0.5 U.L. 0.5 U.L. 1.5 U.L. 0.5 U.L. 10 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. 0.75 U.L. 0.25 U.L. 5 U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW. LOGIC SYMBOL 1 11 12 13 14 3 4 5 6 PL P0 P1 P2 P3 P4 P5 P6 P7 DS Q7 CP Q7 10 2 15 9 7 VCC = PIN 16 GND = PIN 8 http://onsemi.com 2 SN74LS165 LOGIC DIAGRAM 11 12 13 14 3 4 5 6 P0 P1 P2 P3 P4 P5 P6 P7 10 DS 2 CP1 15 CP2 1 PL PRESET Q0 S CP R CLQ0 PRESET Q1 S CP R CL Q1 PRESET S Q2 CP R CLQ2 PRESET S Q3 CP R CLQ3 PRESET Q4 S CP R CLQ4 PRESET S Q5 CP R CLQ5 PRESET S Q6 CP R CLQ6 PRESET Q7 S CP R CL Q7 9 7 VCC = PIN 16 GND = PIN 8 = PIN NUMBERS FUNCTIONAL DESCRIPTION The SN74LS165 contains eight clocked master/slave RS flip-flops connected as a shift register, with auxiliary gating to provide overriding asynchronous parallel entry. Parallel data enters when the PL signal is LOW. The parallel data can change while PL is LOW, provided that the recommended setup and hold times are observed. For clock operation, PL must be HIGH. The two clock inputs perform identically; one can be used as a clock inhibit by applying a HIGH signal. To avoid double clocking, however, the inhibit signal should only go HIGH while the clock is HIGH. Otherwise, the rising inhibit signal will cause the same response as a rising clock edge. The flip-flops are edge-triggered for serial operations. The serial input data can change at any time, provided only that the recommended setup and hold times are observed, with respect to the rising edge of the clock. TRUTH TABLE CP PL 1 L H H H H X L H 2 X Q0 P0 DS Q0 DS Q0 Q1 P1 Q0 Q1 Q0 Q1 Q2 P2 Q1 Q2 Q1 Q2 Q3 P3 Q2 Q3 Q2 Q3 Q4 P4 Q3 Q4 Q3 Q4 Q5 P5 Q4 Q5 Q4 Q5 Q6 P6 Q5 Q6 Q5 Q6 Q7 P7 Q6 Q7 Q6 Q7 Parallel Entry Right Shift No Change Right Shift No Change CONTENTS RESPONSE L H H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial http://onsemi.com 3 SN74LS165 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VO OL Output LOW Voltage 0.35 Input HIGH Current Other Inputs PL Input Other Inputs PL Input IIL IOS ICC Input LOW Current Other Inputs PL Input Short Circuit Current (Note 1) Power Supply Current - 20 0.5 20 60 0.1 0.3 - 0.4 - 1.2 - 100 36 V A IOL = 8.0 mA 0.4 Min 2.0 0.8 - 1.5 Typ Max Unit V V V V V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = - 18 mA VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VCC = MAX, VIN = 2.7 V IIH mA VCC = MAX, VIN = 7.0 V mA mA mA VCC = MAX, VIN = 0.4 V VCC = MAX VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25C) Limits Symbol fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Parameter Maximum Input Clock Frequency Propagation Delay PL to Output Propagation Delay Clock to Output Propagation Delay P7 to Q7 Propagation Delay P7 to Q7 Min 25 Typ 35 22 22 27 28 14 21 21 16 35 35 40 40 25 30 30 25 Max Unit MHz ns ns ns ns VCC = 5.0 V CL = 15 pF F Test Conditions AC SETUP REQUIREMENTS (TA = 25C) Limits Symbol tW tW ts ts ts th trec 1 The Parameter CP Clock Pulse Width PL Pulse Width Parallel Data Setup Time Serial Data Setup Time CP1 to CP2 Setup Time1 Hold Time Recovery Time, PL to CP Min 25 15 10 20 30 0 45 Typ Max Unit ns ns ns ns ns ns ns VCC = 5.0 V Test Conditions role of CP1 and CP2 in an application may be interchanged. http://onsemi.com 4 SN74LS165 DEFINITION OF TERMS: SETUP TIME (ts) -- is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW-to-HIGH in order to be recognized and transferred to the outputs. HOLD TIME (th) -- is defined as the minimum time following the clock transition from LOW-to-HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative hold time indicates that the correct logic level may be released prior to the clock transition from LOW-to-HIGH and still be recognized. RECOVERY TIME (trec) -- is defined as the minimum time required between the end of the PL pulse and the clock transition from LOW-to-HIGH in order to recognize and transfer loaded Data to the Q outputs. AC WAVEFORMS CP1 tW ts CP2 1.3 V tPHL Q7 OR Q7 1.3 V 1/fmax tW tPLH 1.3 V 1.3 V Q7 OR Q7 PL 1.3 V tPLH 1.3 V 1.3 V 1.3 V tPHL 1.3 V Figure 1. Figure 2. Pn ts(H) PL OR CP 1.3 V th(H) 1.3 V ts(L) 1.3 V th(L) 1.3 V PL 1.3 V tW 1.3 V trec 1.3 V CP Figure 3. Figure 4. http://onsemi.com 5 SN74LS165 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE 648-08 ISSUE R -A- 16 9 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M S INCHES MIN MAX 0.740 0.770 0.250 0.270 0.145 0.175 0.015 0.021 0.040 0.70 0.100 BSC 0.050 BSC 0.008 0.015 0.110 0.130 0.295 0.305 0_ 10 _ 0.020 0.040 MILLIMETERS MIN MAX 18.80 19.55 6.35 6.85 3.69 4.44 0.39 0.53 1.02 1.77 2.54 BSC 1.27 BSC 0.21 0.38 2.80 3.30 7.50 7.74 0_ 10 _ 0.51 1.01 B 1 8 F S C L -T- H G D 16 PL SEATING PLANE K J TA M M 0.25 (0.010) M http://onsemi.com 6 SN74LS165 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B-05 ISSUE J -A- NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS MIN MAX 9.80 10.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50 INCHES MIN MAX 0.386 0.393 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.229 0.244 0.010 0.019 16 9 -B- 1 8 P 8 PL 0.25 (0.010) M B S G F K C -T- SEATING PLANE R X 45 _ M D 16 PL M J 0.25 (0.010) TB S A S DIM A B C D F G J K M P R http://onsemi.com 7 SN74LS165 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. PUBLICATION ORDERING INFORMATION North America Literature Fulfillment: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: ONlit@hibbertco.com N. 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